The present disclosure relates generally to forming a semiconductor device on a substrate and, more particularly, to forming a gate structure of a semiconductor device.
Semiconductor device geometries continue to dramatically decrease in size. Today's fabrication processes are routinely producing devices having feature dimensions less than 65 nm. However, solving the problems associated with implementing new process and equipment technology while continuing to satisfy device requirements has become more challenging. For example, metal-oxide-semiconductor (MOS) transistors have typically been formed with polysilicon gate electrodes. Polysilicon has advantageous thermal resistive properties and can allow for formation of self aligned source/drain structures.
However, in order to continually meet performance requirements, there has been a desire to replace the polysilicon gate electrode with a metal gate electrode. One process of implementing metal gates is termed a “gate last” or “replacement gate” methodology. In such a process, a dummy (e.g., sacrificial) polysilicon gate is initially formed, various processes associated with the semiconductor device are performed, and the dummy gate is subsequently removed and replaced with a metal gate. However, care must be taken during the process to provide the adequate work function of the resulting metal gate. Typically however due to processing constraints, one or more of the resultant devices includes both p-type work function metal and n-type work function metal. For example, an NMOSFET will contain both p-type work function metal as well as the n-type work function metal. This may be disadvantageous as the flat band voltage of the work function metal is impacted by the metal having the opposite work function. Thus, what is desired is a semiconductor device and/or method of fabricating thereof that provides for threshold voltage controllability through selection of work function metals.